Understand VHDL and how it is used to describe digital circuits
Introduction to VHDL is a course that someone with no experience or knowledge of VHDL can use to learn and understand the VHDL language. In this course students will learn about all of the different data types associated with the VHDL language. This course focuses on teaching students how the syntax of VHDL is interpreted and how it can be used to design circuits. There are over 8 different examples digital designs implemented in VHDL.
What you’ll learn
- Implement their own VHDL designs on a FPGA / CPLD.
- Interpret a digital design written in VHDL.
- Simulate their own VHDL designs.
- Understanding of the capabilities of VHDL.
Course Content
- Introduction –> 3 lectures • 10min.
- Objects –> 7 lectures • 24min.
- Data Types –> 4 lectures • 1hr 32min.
- Loops and Statements –> 5 lectures • 11min.
- Design Structure –> 4 lectures • 22min.
- Data Flow Design Style –> 5 lectures • 25min.
- Behavioral Design Style –> 3 lectures • 33min.
- Structural Design Style –> 3 lectures • 28min.
- Test Bench Designs –> 2 lectures • 32min.
- Simulations –> 8 lectures • 44min.
- FPGA Development Flow Project Using VHDL –> 8 lectures • 49min.
- Conclusion –> 2 lectures • 3min.
Requirements
Introduction to VHDL is a course that someone with no experience or knowledge of VHDL can use to learn and understand the VHDL language. In this course students will learn about all of the different data types associated with the VHDL language. This course focuses on teaching students how the syntax of VHDL is interpreted and how it can be used to design circuits. There are over 8 different examples digital designs implemented in VHDL.
Course Structure
This course starts out by explaining the background and history of VHDL and it’s uses. Then students will learn about all the different objects and data types associated with VHDL. There are various examples showing the data types in use and how different objects behave in different applications. After learning about the data types and objects, students will then learn about the keywords and syntax of the VHDL language. Then students will learn about all of the different design architectures used in VHDL. Students will also learn how to design a test bench to simulate and verify functionality of their designs. This knowledge will then be used to complete the final project, tying in all facets of the VHDL language.
VHDL Designs
This course has many design examples, upon completing this course students will have their own library of VHDL design they can use and refer to at any time! This design library includes:
- Logical AND gate
- Logical OR gate
- Logical NOR gate
- Logical NAN gate
- Logical XOR gate
- Half Adder
- Full Adder
- D Flip-Flop
- Digital Comparator
- SR (Set Reset) Latch
- 2:1 Multiplexer
- Priority Encoder
Final Project
The final project in the course has students go through the design process of implementing a priority encoder on their very own development board. This project takes students through the various phases of developing a digital design, testing it, and implementing it. Students will be taken through step-by-step everything that is required to get the priority encoder up and running on their development board.
Feel free to message me with any questions before signing up for this course!